Inseto

Wafer Level Services

Wafer Level Capabilities

  • Wafer level solder bumping for fine pitch interconnection
  • Copper pillar and post structures for high current and high reliability applications
  • Redistribution layer (RDL) processing to re route die to an array format
  • Wafer grinding, dicing and metalisation
  • Lead free and customised bump metallurgies
  • Support for silicon, compound semiconductor, and specialty wafers

PacTech GmbH provides comprehensive wafer level packaging (WLP) services, supporting semiconductor and advanced microelectronics applications from prototype through to volume production. PacTech is widely recognised for its expertise in wafer level processes that enable high interconnect density, reduced package size, and improved electrical and thermal performance.

PacTech’s wafer level packaging services are suitable for early stage development work as well as established production programmes. This allows customers to qualify processes, build prototypes, and transition to volume manufacturing without changing suppliers or process routes.

Wafer Level Packaging Capabilities

PacTech provides a broad range of wafer level packaging services designed to support modern device architectures and advanced packaging requirements. Services include, but are not limited to:

  • Wafer level solder bumping for fine pitch interconnection
  • Copper pillar and post structures for high current and high reliability applications
  • Redistribution layer (RDL) processing to re route die to an array format
  • Wafer grinding, dicing and metalisation
  • Lead free and customised bump metallurgies
  • Support for silicon, compound semiconductor, and specialty wafers

These processes enable compact, high performance packages suitable for applications where space, electrical performance, and reliability are critical.

Typical Applications

PacTech wafer level packaging services are widely used across advanced semiconductor devices, RF and microwave components, optoelectronic and sensor technologies, and power and high current applications, as well as automotive and industrial electronics where high reliability, performance, and compact package formats are essential.

By carrying out key interconnection steps at wafer level, customers benefit from improved yield, reduced assembly complexity, and lower overall manufacturing cost.

Speak to Our Technical Team

To discuss wafer level packaging requirements, suitability for your application, or integration with other Inseto supplied processes and materials, please contact the Inseto technical team.

We will work with you to define the most appropriate wafer level packaging solution using PacTech’s proven manufacturing services.

Related Products

Knowledge Base Articles

Further Information

Contact Us

Tel: +44 (0)1264 334505

Email: enquiries@inseto.co.uk

Applications

MEMS Packaging, Camera Module Fabrication, Memory, FO WLP, Flip Chip Bumping, BGA Solder Ball Placement, Smart phones and Tablet CSP Packaging, Bio Medical Device Assembly, Sub Contract Wafer Dicing, Sub Contract Wafer Bumping, Sub Contract Solder Bumping

Industry Segments

Semiconductor Fabrication, Photonics, Bio Medical, Consumer Electronics, Aerospace, Defence

Region

United Kingdom, Ireland & Scandinavia/Nordic Regions: Finland, Sweden, Norway & Denmark, Netherlands, France & Benelux

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